• DocumentCode
    2361264
  • Title

    A simple and efficient concept for setting up multi-VT devices in thin BOx fully-depleted SOI technology

  • Author

    Noel, J.-P. ; Thomas, O. ; Fenouillet-Beranger, C. ; Jaud, M.-A. ; Scheiblin, P. ; Amara, A.

  • Author_Institution
    CEA, MINATEC, Grenoble, France
  • fYear
    2009
  • fDate
    14-18 Sept. 2009
  • Firstpage
    137
  • Lastpage
    140
  • Abstract
    In this paper, an original and simple concept for setting up multi-VT for fully-depleted (FD) silicon-on-insulator (SOI) MOSFETs is presented. Low, standard and high threshold voltage (VT) devices are achieved without degrading the good channel electrostatic control and the low VT dispersion of the FDSOI technology. The concept is based on the use of a thin buried oxide (BOx) combined with the integration of a doped and biased back plane (BP). This was evaluated by TCAD simulations and benchmarked to the LSTP (Low STandby Power) BULK technology in 45 nm technology node. The electrical results highlight the efficiency of the proposed concept. The LVT, SVT and HVT devices show similar results than in the LSTP BULK technology (ION-LVT=1.35timesION-HVT) with ION/IOFF current ratios higher than 6 decades. Moreover, the concept has been applied to a 6T SRAM cell declined in dual versions: HVT and LVT highlighting excellent cell current ratios (47%).
  • Keywords
    CAD; MOSFET; SRAM chips; benchmark testing; low-power electronics; semiconductor doping; silicon-on-insulator; 6T SRAM cell; TCAD simulations; benchmark; biased back plane; channel electrostatic control; doped back plane; high-threshold voltage device; low standby power bulk technology; low-threshold voltage device; silicon-on-insulator MOSFETs; size 45 nm; standard-threshold voltage device; thin BOx fully-depleted SOI technology; thin buried oxide structure; threshold voltage dispersion; Analytical models; CMOS technology; Degradation; Doping; Electrostatics; Leakage current; MOS devices; Random access memory; Silicon on insulator technology; Threshold voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid State Device Research Conference, 2009. ESSDERC '09. Proceedings of the European
  • Conference_Location
    Athens
  • ISSN
    1930-8876
  • Print_ISBN
    978-1-4244-4351-2
  • Electronic_ISBN
    1930-8876
  • Type

    conf

  • DOI
    10.1109/ESSDERC.2009.5331491
  • Filename
    5331491