A sliding memory plane array processor

A mesh-connected array processor for low-level vision tasks is described. Several disadvantages of existing mesh-connected array processors, such as communication overhead between processing elements (PEs), data input/output (I/O) overhead, and complicated interconnections, are alleviated. The sliding memory plane (SliM) array processor, a fine-grained bit-parallel single-instruction multiple-data (SIMD) architecture, achieves higher speeds than existing mesh-connected array processors. In this architecture intermemory communication as well as inter-PE communication can take place without interrupting PEs. In other words, during computation, the contents of all register cells on the sliding memory plane can be shifted simultaneously and in the same direction to the neighboring cells. In addition, the duplicated I/O planes can provide buffering capability. Since communication, I/O and computation occur at the same time, the communication and I/O overhead is greatly diminished. The performance of the SliM shows remarkable improvement over existing machines