Title :
Cu CMP with orbital technology: summary of the experience
Author :
Gotkis, Y. ; Schey, D. ; Alamgir, S. ; Yang, J. ; Holland, K.
Author_Institution :
Adv. Process Dev., Integrated Process Equip. Corp., Phoenix, AZ, USA
Abstract :
The Cu process is becoming increasingly attractive as a future choice for IC technology, using Cu both for plugs and wiring. Single and dual Cu damascene includes multiple use of CMP, both for dielectric planarization and removal of excess field material. CMP performance is therefore of extremely high importance for Cu technology. Orbital polishing is known as an effective CMP technique (Bibby et al., Semicond. FABTECH Asia Special, pp. 38-47, 1997). The advantages of this technique are high material removal uniformity (at 3 mm EE), planarization efficiency, high throughput, small footprint, and low cost of ownership. This paper summarizes our experience in Cu-CMP R&D with IPEC´s Avantgaard 676 and 776 orbital planarizers. Results on consumable screening, process stability and uniformity, analysis of planarization phenomena for heterogeneous surfaces and data on metal line thinning and dielectric erosion, and discussion of some process integration issues are presented
Keywords :
abrasion; chemical mechanical polishing; copper; dielectric thin films; integrated circuit interconnections; integrated circuit metallisation; integrated circuit testing; stability; surface topography; CMP; CMP performance; CMP technique; Cu; Cu CMP; Cu plugs; Cu process; Cu wiring; IC technology; IPEC Avantgaard orbital planarizers; consumable screening; cost of ownership; dielectric erosion; dielectric planarization; dual Cu damascene process; excess field material performance; heterogeneous surfaces; material removal uniformity; metal line thinning; orbital polishing; orbital technology; planarization efficiency; planarization phenomena; process footprint; process integration; process stability; process uniformity; single Cu damascene process; throughput; Conducting materials; Costs; Dielectric materials; Planarization; Plugs; Research and development; Silicon compounds; Surface resistance; Throughput; Wiring;
Conference_Titel :
Advanced Semiconductor Manufacturing Conference and Workshop, 1998. 1998 IEEE/SEMI
Conference_Location :
Boston, MA
Print_ISBN :
0-7803-4380-8
DOI :
10.1109/ASMC.1998.731619
