Channel filters for microelectronic receivers of wireless systems

A short overview of receiver architectures and low-pass filter specifications for wireless systems is reported. Two design procedures of low-pass filters for communication system are discussed. A CMOS transconductance-capacitor (G_m-C) filter with enhanced linearity is presented as the first one. The proposed design is based on a transconductance amplifier with enhanced linearity. For the elimination of the amplifier harmonic level the compensation principle is used. The device was realized as a balanced fifth-order 1 MHz low-pass Bessel filter in 0.35 μm CMOS process. The filter operates with a low supply voltage of +2.5 Volt. Its power consumption is 8.25 mW, the input referred RMS noise is 120 μV (0.01 + 2 MHz), and HD3 (1 V_P-to-P @ 1 MHz) is -54 dB. Alternatively a new approach to the design of high-frequency filters with low power consumption is presented. The idea is to use current mode and voltage mode active elements with enhanced frequency range. These elements are second generation current conveyors and voltage buffers, those are used to implement integrators. The filter is realized as a switched-capacitor circuit based on an integrator chain with multi feedback loops. As an example a CMOS switched-capacitor filter with 1 MHz cut-off frequency is presented. The device was realized as an unbalanced fifth-order low-pass Chebyshev filter in 03 μm CMOS process. The filter operates with supply voltage varying from +2.5 V to +3 V. Depending on the supply voltage its power consumption is from 3 mW to 10 mW, the input referred RMS noise is 1.9 mV (0.02 + 2 MHz @ +3 V), and HD3 (2 V_P-to-P @ 900 kHz @ +3 V) is -54 dB.