A Reconfigurable “ SFMD Architecture ” For a Class of Signal Processing Applications

The fastest programmable DSP processors are unable to meet the speed requirements of many advanced signal processing applications. SlMD machines have been a preferred solution in such applications because of their inherent spatial parallelism. In such machines, a control unit (CU) broadcasts simple machine instructions simultaneously to a number of processing elements (PEs) executing the same instruction on different data The performance of such architectures can be vastly enhanced if the PEs can execute at the level of signal processing function rather than low level machine instruction. This can be made possible if the PEs are so designed that they can receive and execute functional level instruction from the CU instead of simple machine level instruction. FPGAs have emerged as high performance flexible hardware for many signal processing applications but they are not optimised for any particular application. Hence, they can not offer highest possible performance at lowest silicon cost for a given signal processing algorithm. This paper addresses these issues by introducing a new reconfigurable DSP processor, "single function multiple data (SFMD)" which eliminates the drawbacks of conventional SIMD machines and offers a balance between flexibility, reconfiguration latency and performance