Author :
Chiarella, T. ; Witters, L. ; Mercha, A. ; Kerner, C. ; Dittrich, R. ; Rakowski, M. ; Ortolland, C. ; Ragnarsson, L.A. ; Parvais, B. ; De Keersgieter, A. ; Kubicek, S. ; Redolfi, A. ; Rooyackers, R. ; Vrancken, C. ; Brus, S. ; Lauwers, A. ; Absil, P. ; Bi
Abstract :
The multi-gate architecture is considered as a key enabler for further CMOS scaling. FinFETs can readily be manufactured on SOI or bulk substrates. We report for the first time an extensive benchmark of their critical electrical figures of merit. Both alternatives show better scalability than PLANAR CMOS and exhibit similar intrinsic device performance. Introducing SOI substrates and low doped fins results in lower junction capacitance, higher mobility and voltage gain with reduced mismatch. Using an optimized integration to minimize parasitics we demonstrate high-performing FinFET ring-oscillators with delays down to 10ps/stage for both SOI and bulk FinFETs and working SRAM cells at VDD=1.0V.
Keywords :
CMOS integrated circuits; MOSFET circuits; semiconductor device manufacture; CMOS scaling; SOI substrates; SRAM cells; high-performing FinFET ring-oscillators; intrinsic device performance; junction capacitance; low doped fins; multi-gate architecture; voltage 1 V; voltage gain; Circuits; Degradation; Delay; Electronic mail; FinFETs; Manufacturing; Parasitic capacitance; Random access memory; Scalability; Voltage;
