Title :
On the integration of Ta2O5 as a gate dielectric in sub-0.18 μm CMOS processes
Author :
Devoivre, T. ; Papadas, C. ; Setton, M. ; Sandler, N. ; Vallier, L. ; Bouras, I.
Author_Institution :
Central R&D Technol., ST Microelectron., Crolles, France
Abstract :
In this paper, a feasibility study on the incorporation of Ta2O5 as a gate dielectric in sub-0.18 μm CMOS processes is presented. The advantages of such a structure are investigated and appear consistent with low voltage/high performance applications. The main technological features associated with this incorporation are discussed (Ta2O5 densification and interfacial oxide, gate electrode and related features, etching, TiN behaviour, etc.) and a full process flow with few modifications with respect to standard CMOS is presented. With this flow, real devices were processed and their electrical characteristics are shown. These results are close to current SiO2 MOS results, and are therefore promising for sub-2.5 nm equivalent SiO2 thickness gate dielectrics
Keywords :
CMOS integrated circuits; chemical interdiffusion; densification; dielectric thin films; diffusion barriers; etching; integrated circuit interconnections; integrated circuit metallisation; interface structure; tantalum compounds; 0.18 micron; 2.5 nm; CMOS processes; SiO2; Ta2O5 densification; Ta2O5 gate dielectric; Ta2O5 gate dielectric integration; Ta2O5-Si; TiN; TiN behaviour; electrical characteristics; equivalent SiO2 thickness; etching; feasibility study; gate dielectrics; gate electrode; interfacial oxide; low voltage/high performance applications; process flow; process modifications; standard CMOS process; technological features; CMOS process; CMOS technology; Capacitance; Dielectric materials; Electrodes; Leakage current; Low voltage; Microelectronics; Permittivity; Tin;
Conference_Titel :
Advanced Semiconductor Manufacturing Conference and Workshop, 1998. 1998 IEEE/SEMI
Conference_Location :
Boston, MA
Print_ISBN :
0-7803-4380-8
DOI :
10.1109/ASMC.1998.731642
