A 3-D re-configurable image processing element

Image processing is generally computationally intensive, and has, traditionally, required high-speed ASICs to produce acceptable real-time speeds. The use of a general-purpose computer (GPC) allows simple verification of an algorithm, but not usually real-time processing. Using an ASIC accelerator with a GPC can yield good performance, however it may have limited functionality due to the pre-defined architecture of the ASIC. Here we present a novel, general-purpose, real-time, re-configurable hardware accelerator with an architecture suitable for rapid image processing. The system, developed as part of an EPSRC-funded project, will also be implemented as a single `device´ using 3D multi-chip module technology