DocumentCode :
2363139
Title :
Designing hierarchical hardware for efficient timer handling
Author :
Björkman, Mats
Author_Institution :
Dept. of Comput. Syst., Uppsala Univ., Sweden
fYear :
1990
fDate :
30 Sep-2 Oct 1990
Firstpage :
149
Lastpage :
152
Abstract :
The author describes the design of a timer handler coprocessor, the 6pm (Swedish Institute of Computer Science or SICS protocol machine) GMT (general manager of timers). In distributed systems, internode communication needs to have both high throughput and low end-to-end delay. For real-time applications, a guaranteed maximum delay is also important. Special-purpose communication processors (protocol machines) could be used in the nodes to speed up protocol execution. The design of the 6 pm which uses special-purpose coprocessors for well-defined subactivities, is described. This coprocessor is designed for good average and worst-case performance on a high-speed network. Performance estimations based on instructions-counting simulations are given. These simulations show that an implementation of the 6 pm GMT on an 88 K processor will be able to handle all timers on a gigabit network
Keywords :
delays; distributed processing; protocols; satellite computers; timing circuits; 6 pm GMT; SICS protocol machine; average case performance; distributed systems; efficient timer handling; end-to-end delay; general manager of timers; hierarchical hardware design; instructions-counting simulations; maximum delay; protocol machines; real-time applications; special-purpose coprocessors; timer handler coprocessor; worst-case performance; Computer science; Context; Coprocessors; Delay; Distributed computing; Hardware; High-speed networks; Protocols; Silicon carbide; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Distributed Computing Systems, 1990. Proceedings., Second IEEE Workshop on Future Trends of
Conference_Location :
Cairo
Print_ISBN :
0-8186-2088-9
Type :
conf
DOI :
10.1109/FTDCS.1990.138310
Filename :
138310
Link To Document :
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