DocumentCode :
2363348
Title :
Low power soft output Viterbi decoder scheme for turbo code decoding
Author :
Lin, Lang ; Tsui, Chi Ying ; Cheng, Roger S.
Author_Institution :
Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, Hong Kong
Volume :
2
fYear :
1997
fDate :
9-12 Jun 1997
Firstpage :
1369
Abstract :
Turbo codes, which are new forward error-correcting codes (FEC), represent a prospective coding scheme for future wireless communication. In this paper, we propose two schemes to reduce the power consumption of the register-exchange soft output Viterbi decoder (SOVD) for turbo code decoding. The first scheme employs the notion of the scarce state transition (SST) which changes the data representation during decoding. The second scheme simply changes the bit representation in the survivor memory unit (SMU) of the decoder. Simulation results show that up to 70% reduction in bit transitions in the SMU can be achieved by both schemes when decoding a 16-state turbo code
Keywords :
Viterbi decoding; concatenated codes; convolutional codes; error correction codes; bit representation; data representation; forward error-correcting code; low power decoder scheme; power consumption reduction; register-exchange decoder; scarce state transition; soft output Viterbi decoder scheme; survivor memory unit; turbo code decoding; wireless communication; Codecs; Delay; Energy consumption; Error correction codes; Forward error correction; Iterative decoding; Switching circuits; Turbo codes; Viterbi algorithm; Wireless communication;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
Print_ISBN :
0-7803-3583-X
Type :
conf
DOI :
10.1109/ISCAS.1997.622125
Filename :
622125
Link To Document :
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