Real-Time implementation of a SPLL for FACTS

This paper presents a real-time implementation of a software phase-locked loop (SPLL) for use within FACTS systems. The FACTS phase locked loops (PLLs) main characteristics and the disturbances impact over their performance are reviewed making special emphasis on the weak points of the usual three-phase trans-vector-type PLLs. These weak points are mainly slow response under low amplitude AC inputs and three-phase unbalances. Recently some alternatives, specially the adaptive SPLL, solved these typical trans-vector issues. However, the discrete implementation of adaptive SPLL in a programmable device like a microcontroller, a DSP or a FPGA seems very complex. In this work a double-loop SPLL has been developed with the aim of reducting the complexity of a discrete implementation and without losing performance with respect to the adaptive SPLL. The proposed double-loop SPLL has been implemented in real-time using Matlab/Simulink and the fast prototyping platform dSpace DS1103; its high performance and feasibility are shown in the simulation and real-time implementation sections