Design and verification based on assertions: some statistics

Author

Cortéz, J. ; Torres, D.

Author_Institution

Dept. of Electr. Eng., CINVESTAV-IPN, Guadalajara, Mexico

fYear

2005

fDate

7-9 Sept. 2005

Firstpage

132

Lastpage

135

Abstract

Usually, the assertion based verification (ABV) is used for the formal verification of digital design. In this work, we show that it can be used also for the code implementation in a hardware description language (HDL), saving time and improving the whole design process. Property specification language (PSL) was used for the written of assertions for a specific circuit. Finally, a set of properties for finite states machines (FSM) was established.

Keywords

finite state machines; formal specification; formal verification; hardware description languages; assertion based verification; code implementation; digital design; finite state machines; formal verification; hardware description language; property specification language; Cities and towns; Computer science; Error correction; Formal verification; Hardware design languages; IEEE catalog; Proposals; Statistics; Assertion Based Verification; Finite State Machines; Formal Verification; Semi-formal Specification;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Electronics Engineering, 2005 2nd International Conference on

Print_ISBN

0-7803-9230-2

Type

conf

DOI

10.1109/ICEEE.2005.1529590

Filename

1529590

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2363790