A four-level-metal fully planarized interconnect technology for dense high performance logic and SRAM applications

Author

Uttecht, Ronald R. ; Geffken, Robert M.

Author_Institution

IBM Gen. Technol. Div., Essex Junction, VT, USA

fYear

1991

fDate

11-12 Jun 1991

Firstpage

20

Lastpage

26

Abstract

The authors describe a four-level-metal (4LM) interconnect technology used to wire high-density, high-performance logic and SRAM chip designs. Process features includes oxide planarization under all metal levels, tungsten studs for contacts and interlevel vias, layered titanium and aluminium-0.5% copper metal lines patterned by reactive ion etch (RIE), and fusible metal links for redundancy applications. Functional 300K circuit ASIC logic test sites (4LM) and 256K SRAMs (3LM) have been fabricated in both 125-mm and 200-mm wafer sizes. Process details are described along with the results of standard electrical tests and reliability stresses

Keywords

SRAM chips; integrated circuit technology; integrated logic circuits; metallisation; redundancy; ASIC logic test sites; RIE; SRAM applications; Ti-AlCu; W studs; dense high performance logic; electrical tests; four-level-metal; fusible metal links; high-density; interlevel vias; layered Ti/Al-Cu metal lines; oxide planarization; planarized interconnect technology; reactive ion etch; redundancy applications; reliability stresses; Copper; Etching; Integrated circuit interconnections; Logic design; Planarization; Redundancy; SRAM chips; Titanium; Tungsten; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Multilevel Interconnection Conference, 1991, Proceedings., Eighth International IEEE

Conference_Location

Santa Clara, CA

Print_ISBN

0-87942-673-X

Type

conf

DOI

10.1109/VMIC.1991.152961

Filename

152961