Asynchronous design in dynamic CMOS

Author

Ahmed, J. ; Zaky, S.G.

Author_Institution

Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada

Volume

fYear

1997

fDate

25-28 May 1997

Firstpage

528

Abstract

The design for dynamic CMOS cells that can be used as building blocks in an asynchronous pipeline are discussed in this paper. The proposed circuit elements are variations on TSPC logic using Sutherland´s micropipeline structure combined with dual rail logic to detect operation completion. The resulting cell occupies more area than a TSPC cell, but has higher functionality because of the built-in data flow control mechanisms provided by the handshake signaling of the micropipeline structure

Keywords

CMOS logic circuits; asynchronous circuits; integrated circuit design; logic design; pipeline processing; TSPC logic; asynchronous design; built-in data flow control; completion detection; dual rail logic; dynamic CMOS cell; handshake signaling; micropipeline structure; Asynchronous circuits; CMOS logic circuits; Circuit testing; Clocks; Frequency synchronization; Logic circuits; Pipelines; Rails; Signal design; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 1997. Engineering Innovation: Voyage of Discovery. IEEE 1997 Canadian Conference on

Conference_Location

St. Johns, Nfld.

ISSN

0840-7789

Print_ISBN

0-7803-3716-6

Type

conf

DOI

10.1109/CCECE.1997.608275

Filename

608275

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2364376