A high reliability triple metal process for high performance application specific circuits

Author

Pramanik, Dipankar ; Jain, Vivek ; Chang, K.Y.

Author_Institution

VLSI Technol. Inc., San Jose, CA, USA

fYear

1991

fDate

11-12 Jun 1991

Firstpage

27

Lastpage

33

Abstract

A triple metal process for high performance, high reliability application specific CMOS circuits is described. Key features of this process are identical pitches for all three levels of metal, layered metal for high electromigration resistance of interconnects and vias, planarised dielectrics, and very good hot carrier reliability of submicron MOS devices

Keywords

CMOS integrated circuits; application specific integrated circuits; circuit reliability; electromigration; hot carriers; integrated circuit technology; metallisation; ASIC metallisation; IC interconnection; application specific CMOS circuits; electromigration resistance; high reliability; hot carrier reliability; interconnects; planarised dielectrics; submicron MOS devices; triple metal process; vias; Application specific integrated circuits; CMOS process; CMOS technology; Dielectrics; Electromigration; Electrons; Integrated circuit interconnections; Integrated circuit reliability; Routing; Surfaces;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Multilevel Interconnection Conference, 1991, Proceedings., Eighth International IEEE

Conference_Location

Santa Clara, CA

Print_ISBN

0-87942-673-X

Type

conf

DOI

10.1109/VMIC.1991.152962

Filename

152962