• DocumentCode
    2364732
  • Title

    A highly-efficient BiCMOS cascode Class-E power amplifier using both envelope-tracking and transistor resizing for LTE-like applications

  • Author

    Li, Yan ; Wu, Ruili ; Lopez, Jerry ; Lie, Donald Y C

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Texas Tech Univ., Lubbock, TX, USA
  • fYear
    2011
  • fDate
    9-11 Oct. 2011
  • Firstpage
    142
  • Lastpage
    145
  • Abstract
    This paper presents the design of a SiGe differential cascode power amplifier (PA) to perform the envelope-tracking (ET) along with transistor resizing for efficiency enhancement for the 16QAM LTE. A new parallel-circuit class-E PA model is developed to analyze and design the cascode PA. The analytic results are compared with SPICE simulation and measurement data to provide circuit design insights. Measurement shows the ET-based PA system reaches an overall power-added-efficiency (PAE) of 38% at its 1 dB compression point (P1dB) of 22 dBm for its high power mode. Additionally, at the low power mode, some of the transistor cells can be disabled by the integrated MOSFET switches, and the overall PAE is improved by 4-5% at ≥4 dB back-off from its P1dB. This ET-based cascode PA satisfies the LTE 16QAM linearity specs without needing predistortions.
  • Keywords
    BiCMOS analogue integrated circuits; Ge-Si alloys; Long Term Evolution; field effect transistor switches; power amplifiers; quadrature amplitude modulation; 16QAM LTE; ET-based PA system; LTE-like applications; Long-Term-Evolution; PAE; SPICE measurement data; SPICE simulation; SiGe; circuit design; differential cascode power amplifier; efficiency 38 percent; envelope-tracking; highly-efficient BiCMOS cascode Class-E power amplifier; integrated MOSFET switches; parallel-circuit class-E PA model; power-added-efficiency; transistor cells; transistor resizing; BiCMOS integrated circuits; CMOS integrated circuits; Linearity; Modulation; Power amplifiers; Silicon germanium; Transistors; LTE; SiGe BiCMOS power amplifier (PA); envelope-tracking (ET); parallel-circuit class-E PA model; transistor resizing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 2011 IEEE
  • Conference_Location
    Atlanta, GA
  • ISSN
    1088-9299
  • Print_ISBN
    978-1-61284-165-6
  • Type

    conf

  • DOI
    10.1109/BCTM.2011.6082767
  • Filename
    6082767