A new design of XOR-XNOR gates for low power application

Author

Ahmad, Nabihah ; Hasan, Rezaul

Author_Institution

Fac. of Electr. & Electron., Univ. Tun Husseion Onn Malaysia, Batu Pahat, Malaysia

fYear

2011

fDate

25-27 April 2011

Firstpage

45

Lastpage

49

Abstract

XOR and XNOR gate plays an important role in digital systems including arithmetic and encryption circuits. This paper proposes a combination of XOR-XNOR gate using 6-transistors for low power applications. Comparison between a best existing XOR-XNOR have been done by simulating the proposed and other design using 65nm CMOS technology in Cadence environment. The simulation results demonstrate the delay, power consumption and power-delay product (PDP) at different supply voltages ranging from 0.6V to 1.2V. The results show that the proposed design has lower power dissipation and has a full voltage swing.

Keywords

CMOS logic circuits; arithmetic; cryptography; logic design; logic gates; low-power electronics; 6-transistors; Cadence environment; XNOR gate; XOR gate; arithmetic circuits; digital systems; encryption circuits; power consumption; power-delay product; size 65 nm; voltage 0.6 V to 1.2 V; CMOS integrated circuits; Delay; Inverters; Logic gates; Power dissipation; Simulation; Transistors; XOR-XNOR gate; delay; low power;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Devices, Systems and Applications (ICEDSA), 2011 International Conference on

Conference_Location

Kuala Lumpur

ISSN

2159-2047

Print_ISBN

978-1-61284-388-9

Type

conf

DOI

10.1109/ICEDSA.2011.5959039

Filename

5959039