• DocumentCode
    2365007
  • Title

    Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC

  • Author

    Yotsuyanagi, Hiroyuki ; Hashizume, Masaki ; Tsutsumi, Toshiyuki ; Yamazaki, Koji ; Aikyo, Takashi ; Higami, Yoshinobu ; Takahashi, Hiroshi ; Takamatsu, Yuzo

  • Author_Institution
    Inst. of Technol. & Sci., Univ. of Tokushima, Tokushima
  • fYear
    2009
  • fDate
    5-9 Jan. 2009
  • Firstpage
    91
  • Lastpage
    96
  • Abstract
    Open faults are difficult to test since the voltage at the floating line is unpredicted and depends on the voltage at the adjacent lines. The modeling for open faults with considering adjacent lines has been proposed. In this work, the 90 nm IC is designed and fabricated to evaluate how the voltage at adjacent lines affect the defective line. The open fault macros with a transmission gate and with an intentional break are included in the IC. The nine lines are placed in parallel in three layers to observe the effect of the coupling capacitance when an open occurs. The benchmark circuits with the open fault macro are also included in the IC. The simulation and experimental results show that the relationship between the floating line and the adjacent lines. The experimental results are also compared with the open fault model that calculate the weighted sum of voltages at the adjacent lines.
  • Keywords
    capacitance; electrical faults; integrated circuits; macros; IC; adjacent signal lines; coupling capacitance; fault effect; floating line; open fault macro; transmission gate; Capacitance; Circuit faults; Coupling circuits; Design engineering; Integrated circuit testing; Logic testing; Signal design; Very large scale integration; Voltage; Wires; adjacent lines; coupling capacitance; defect-based testing; open fault;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 2009 22nd International Conference on
  • Conference_Location
    New Delhi
  • ISSN
    1063-9667
  • Print_ISBN
    978-0-7695-3506-7
  • Type

    conf

  • DOI
    10.1109/VLSI.Design.2009.60
  • Filename
    4749658