100KHz-20MHz Programmable Subthreshold G_m-C Low-Pass Filter in 0.18µ-m CMOS

This paper proposes a modified, inverter based transconductor using double CMOS pair for implementation of biquad Gm-C low-pass filter with bandwidth tunable from 100 kHz to 20 MHz. This bandwidth range meets the requirements of zero IF receivers for wireless applications. Major contributions of this paper are proposal for operating the Gm stage in sub-threshold region so as to minimize the power dissipation, proposal for switching in both dummy stages and load capacitors (accumulation MOS-Capacitor) to maintain constant capacitance. The centre frequency of the filter is varied by switching in different Gm cells. The proposed filter is designed and implemented on TSMC-0.18 mum CMOS process with 1.8 V supply using G_m/I_d design methodology. The simulation results demonstrate the tunability of the centre frequency from 100 KHz to 20 MHz. The power dissipated by the filter is 12 muW and 900 muW at 100 KHz and 20 MHz respectively. The SFDR over the entire band is 57 dB. The proposed approach guarantees the upper bound on THD to be -40 dB for 300 mVpp signal swing. The use of inverters with double CMOS pair results in 34 dB higher PSRR compared to those using push pull inverter.