Low-power embedded microprocessor design

Author

Piguet, C. ; Schneider, T. ; Masgonty, J.-M. ; Arm, C. ; Durand, S. ; Stegers, M.

Author_Institution

Centre Suisse d´´Electronique et de Microtechnique SA, Neuchatel, Switzerland

fYear

1996

fDate

2-5 Sep 1996

Firstpage

600

Lastpage

605

Abstract

Low-power consumption has emerged as a very important issue in the design of integrated circuits in CMOS technology. The basic idea behind low-power RISC-like architectures is to reduce the number of executed instructions and clock cycles for the execution of a given task. In addition to these architectural issues, important power savings have been obtained by lowering the supply voltage, by pipelining, by adopting gated clock techniques as well as by using hierarchical memories

Keywords

CMOS integrated circuits; microprocessor chips; real-time systems; reduced instruction set computing; CMOS technology; clock cycles; gated clock techniques; hierarchical memories; low-power RISC-like architectures; low-power embedded microprocessor design; power savings; CMOS integrated circuits; CMOS technology; Clocks; Design methodology; Energy consumption; Integrated circuit technology; Microprocessors; Reduced instruction set computing; Registers; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

EUROMICRO 96. Beyond 2000: Hardware and Software Design Strategies., Proceedings of the 22nd EUROMICRO Conference

Conference_Location

Prague

ISSN

1089-6503

Print_ISBN

0-8186-7487-3

Type

conf

DOI

10.1109/EURMIC.1996.546487

Filename

546487