Title :
A 4Gbps 0.57pJ/bit Process-Voltage-Temperature Variation Tolerant All-Digital True Random Number Generator in 45nm CMOS
Author :
Srinivasan, Suresh ; Mathew, Sanu ; Erraguntla, Vasantha ; Krishnamurthy, Ram
Author_Institution :
Circuits Res. Lab., Intel Corp., Bangalore
Abstract :
This paper describes an all-digital on-die true random number generator implemented in 45 nm CMOS technology, with random bit throughput of 4 Gbps and total energy consumption of 0.57 pJ/bit. A 2-step tuning mechanism enables robust operation in the presence of up to 20% fabrication-time process variation as well as immunity to run-time voltage and temperature fluctuation. The 100% use of digital components enables a compact layout occupying 1024 mum2 with high entropy/bit of 0.94, and scalable operation down to 0.5 V, while passing all NIST RNG tests.
Keywords :
CMOS integrated circuits; random number generation; 2-step tuning mechanism; CMOS; NIST RNG tests; all-digital on-die true random number generator; process-voltage-temperature variation tolerant random number generator; CMOS process; CMOS technology; Energy consumption; Entropy; Random number generation; Robustness; Runtime; Temperature; Throughput; Voltage fluctuations; All-digital True Random Number Generator; PVT-Variation Tolerant;
Conference_Titel :
VLSI Design, 2009 22nd International Conference on
Conference_Location :
New Delhi
Print_ISBN :
978-0-7695-3506-7
DOI :
10.1109/VLSI.Design.2009.69