• DocumentCode
    236569
  • Title

    An Implementation of Block Conjugate Gradient Algorithm on CPU-GPU Processors

  • Author

    Hao Ji ; Sosonkina, Masha ; Yaohang Li

  • Author_Institution
    Dept. of Comput. Sci., Old Dominion Univ., Norfolk, VA, USA
  • fYear
    2014
  • fDate
    17-17 Nov. 2014
  • Firstpage
    72
  • Lastpage
    77
  • Abstract
    In this paper, we investigate the implementation of the Block Conjugate Gradient (BCG) algorithm on CPU-GPU processors. By analyzing the performance of various matrix operations in BCG, we identify the main performance bottleneck in constructing new search direction matrices. Replacing the QR decomposition by eigendecomposition of a small matrix remedies the problem by reducing the computational cost of generating orthogonal search directions. Moreover, a hybrid (offload) computing scheme is designed to enables the BCG implementation to handle linear systems with large, sparse coefficient matrices that cannot fit in the GPU memory. The hybrid scheme offloads matrix operations to GPU processors while helps hide the CPU-GPU memory transaction overhead. We compare the performance of our BCG implementation with the one on CPU with Intel Xeon Phi coprocessors using the automatic offload mode. With sufficient number of right hand sides, the CPU-GPU implementation of BCG can reach speedup of 2.61 over the CPU-only implementation, which is significantly higher than that of the CPU-Intel Xeon Phi implementation.
  • Keywords
    conjugate gradient methods; graphics processing units; multiprocessing systems; performance evaluation; BCG algorithm; CPU-GPU memory transaction; CPU-GPU processors; CPU-Intel Xeon Phi coprocessors; QR decomposition; automatic offload mode; block conjugate gradient algorithm; hybrid computing scheme; linear systems; offload computing scheme; sparse coefficient matrices; Clocks; Coprocessors; Data transfer; Graphics processing units; Matrix decomposition; Sparse matrices; Block Conjugate Gradient; Multi-core CPU; Graphics Processing Unit; Intel Xeon Phi; Performance Evaluation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Hardware-Software Co-Design for High Performance Computing (Co-HPC), 2014
  • Conference_Location
    New Orleans, LA
  • Type

    conf

  • DOI
    10.1109/Co-HPC.2014.10
  • Filename
    7017966