Title :
Simultaneous Routing and Feedthrough Algorithm to Decongest Top Channel
Author :
Prasad, Santasriya ; Kumar, Anuj
Author_Institution :
Cadence Design Syst., San Jose, CA
Abstract :
In macrocell based SoC design, a routing plan to decongest top channel is an important step during floor planning. While previous approaches attempt at reducing congestion of chip as a whole, there is no attempt to specifically decongest top channel. We present an algorithmic approach to decongest top channel by using very few feedthroughs. Results show that compared to conventional methods, we can decongest top channel by using 20% lesser feedthrough buffers, and better top channel routing resource utilization.
Keywords :
VLSI; circuit layout; microprocessor chips; network routing; system-on-chip; feedthrough algorithm; floor planning; macrocell based SoC design; simultaneous routing; top channel routing resource utilization; Algorithm design and analysis; Assembly; Circuits; Joining processes; Logic design; Macrocell networks; Pins; Routing; Timing; Very large scale integration; Congestion; Feedthrough; Routing;
Conference_Titel :
VLSI Design, 2009 22nd International Conference on
Conference_Location :
New Delhi
Print_ISBN :
978-0-7695-3506-7
DOI :
10.1109/VLSI.Design.2009.83
