Title :
Blocking voltage design consideration for deep trench MOS gate high power devices
Author :
Matsushita, Kenichi ; Omura, Ichiro ; Ogura, Tsuneo
Author_Institution :
Res. & Dev. Center, Toshiba Corp., Kawasaki, Japan
Abstract :
This paper describes, for the first time, the possibility of realizing a deep trench gate device with high blocking voltage. For a trench gate device with 4.5 kV blocking voltage, the influence of the trench gate geometrical parameters on the breakdown voltage is analyzed using the two-dimensional breakdown voltage simulator TONADDE II B. The breakdown voltage decreases as the p-base width increases. On the other hand, the breakdown voltage increases as the trench gate width increases. The breakdown voltage is independent of the trench gate depth from the p-n junction in the region from 8 to 20 μm. Assuming that the trench gate width is 1 μm, the maximum p-base width to realize 4.5 kV blocking voltage is about 6 μm. Therefore, it is concluded that a 4.5 kV blocking voltage of a deep trench gate device is attainable by the present process technology
Keywords :
MIS devices; power semiconductor devices; semiconductor device models; 4.5 kV; TONADDE II B; blocking voltage; breakdown voltage; deep trench MOS gate high power device; design; geometrical parameters; p-base; p-n junction; two-dimensional simulation; Analytical models; Breakdown voltage; Charge carrier processes; Electric breakdown; Ionization; P-n junctions; Power semiconductor devices; Solid modeling; Thyristors; Voltage control;
Conference_Titel :
Power Semiconductor Devices and ICs, 1995. ISPSD '95., Proceedings of the 7th International Symposium on
Conference_Location :
Yokohama
Print_ISBN :
0-7803-2618-0
DOI :
10.1109/ISPSD.1995.515045