Title :
Linewidth control effects on MOSFET ESD robustness
Author :
Voldman, S. ; Never, J. ; Holmes, S. ; Adkisson, J.
Author_Institution :
Microelectron. Div., IBM Corp., Essex Junction, VT, USA
Abstract :
This paper advances state-of-the-art design layout considerations for deep sub-micron (0.25-μm) advanced single and stacked MOSFETs by addressing linewidth control effects on MOSFET ESD robustness. Advanced failure analysis tools are used to demonstrate linewidth bias. ESD robustness as a function of gate-to-gate spacings is addressed for the first time.
Keywords :
CMOS integrated circuits; MOSFET; electrostatic discharge; failure analysis; integrated circuit reliability; integrated circuit testing; photolithography; 0.25 micron; MOSFET ESD robustness; advanced single MOSFETs; deep sub-micron technology; design layout considerations; failure analysis tools; gate-to-gate spacings; linewidth bias; linewidth control effects; stacked MOSFETs; CMOS integrated circuits; Electrostatic discharges; Failure analysis; Integrated circuit reliability; Integrated circuit testing; MOSFETs; Photolithography;
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium, 1996. Proceedings
Print_ISBN :
1-878303-69-4
DOI :
10.1109/EOSESD.1996.865131
