Immediate elimination of gross ESD failures in PLCC MECL product line through innovative techniques

Author

Almazar, Rudy ; Hoffman, Barry

Author_Institution

Motorola Philippines Inc., Philippines

fYear

1996

fDate

10-12 Sept. 1996

Firstpage

110

Lastpage

116

Abstract

Sudden gross ESD failures occurred on MECL 10 H 20 LDS PLCC devices. This affected the yield with deterioration by 22× and electrical AOQ from permanent six-sigma to 170×. These problems influenced the cycle time, with rapid deterioration; as a result, the whole manufacturing process of 10 H devices was suspended. Through charge mapping, statistical experiments, and innovative techniques, the process inducing ESD damage was narrowed down and the root cause immediately corrected. This resulted in the fast restoration of the PLCC 10 H assembly and test operation.

Keywords

bipolar logic circuits; electrostatic discharge; emitter-coupled logic; failure analysis; integrated circuit measurement; integrated circuit packaging; integrated circuit reliability; integrated circuit yield; plastic packaging; statistical analysis; MECL 10 H 20 LDS PLCC devices; PLCC MECL product line; assembly; charge mapping; cycle time; electrical AOQ; gross ESD failures; statistical experiments; yield; Bipolar transistor logic devices; Electrostatic discharges; Emitter coupled logic; Failure analysis; Integrated circuit measurements; Integrated circuit packaging; Integrated circuit reliability; Plastic packaging; Statistics; Yield estimation;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Overstress/Electrostatic Discharge Symposium, 1996. Proceedings

Print_ISBN

1-878303-69-4

Type

conf

DOI

10.1109/EOSESD.1996.865132

Filename

865132