DocumentCode
2366690
Title
System-Level Vulnerability Estimation for Data Caches
Author
Haghdoost, Alireza ; Asadi, Hossein ; Baniasadi, Amirali
Author_Institution
Dept. of Comput. Eng., Sharif Univ. of Technol., Tehran, Iran
fYear
2010
fDate
13-15 Dec. 2010
Firstpage
157
Lastpage
164
Abstract
Over the past few years, radiation-induced transient errors, also referred to as soft errors, have been a severe threat to the data integrity of high-end and mainstream processors. Recent studies show that cache memories are among the most vulnerable components to soft errors within high-performance processors. Accurate modeling of the Vulnerability Factor (VF) is an essential step towards developing cost-effective protection techniques for cache memory. Although Fault Injection (FI) techniques can provide relatively accurate VF estimations they are often very time consuming. To overcome the limitation, recent analytical models were proposed to compute the cache VF in a timely fashion. In this paper, we extend previous work and propose an alternative analytical model to compute System-level Vulnerability Factor (SVF) for both write-through and write-back data caches. In our proposed analytical model, we take into account both read frequency and error masking to compute system-level vulnerability of data cache. Previously suggested modeling techniques overlook the issues of read frequency and error masking, mainly focusing on time periods in which an error could propagate in the system. In this work we show that overlooking these two parameters can significantly impact the system-level VFs for data caches. We report our estimations for SPEC´2K benchmarks and compare to previously suggested models. Our experimental results show that the proposed modeling technique changes previous VF estimations by up to 40%.
Keywords
cache storage; fault tolerant computing; data caches; fault injection techniques; radiation induced transient errors; system level vulnerability estimation; vulnerability factor; Architectural vulnerability factor; Cache memory; System level vulnerability estimation;
fLanguage
English
Publisher
ieee
Conference_Titel
Dependable Computing (PRDC), 2010 IEEE 16th Pacific Rim International Symposium on
Conference_Location
Tokyo
Print_ISBN
978-1-4244-8975-6
Electronic_ISBN
978-0-7695-4289-8
Type
conf
DOI
10.1109/PRDC.2010.9
Filename
5703240
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