Architectural, system level and protocol level techniques for power optimization for networked embedded systems

Summary form only given. Dynamic power management (DPM) entails employing strategies that yield acceptable trade-off between power/energy usage and their performance penalties. These include heuristic shutdown policies, prediction-based shutdown policies, multiple voltage scaling and stochastic modeling based policy optimization. On the other hand, architectural techniques for power savings include application specific techniques for multi-media hardware systems, and generic techniques like clock gating, on-line profiling based monitoring and control etc. Other paradigms of architectures such as network on chip (NoCs) target power optimization as well. Protocol level power optimization methods include generic techniques employed in wireless standard protocols, as well as techniques specific to multi-media traffic. DPM strategies get increasingly sophisticated due to improved power manageability of hardware components. In this context, there is a positive feedback in action. Power management techniques show the potential for power savings, and this pushes hardware developers to support more advanced (finer grained and lower overhead) power management modes. In this tutorial, we provide an overview of three main issues in three segments, namely, architecture level, system level and protocol level techniques of power minimization and management, how they influence each other. However, we do not concentrate on low power VLSI techniques.