Methodology for layout design and optimization of ESD protection transistors

A design methodology for multiple-fingered CMOS electrostatic discharge (ESD) protection transistors is presented. The methodology employs empirical modeling to predict the current-voltage (I-V) characteristics and ESD withstand level of a circuit given the circuit´s layout parameters. Transmission-line pulsing (TLP) is used to characterize the transient I-V response of a set of test structures for a given process technology, with the results of this testing used to build the model. A key step in predicting human-body model (HBM) robustness is the correlation of TLP withstand current to HBM withstand voltage. Identification of an integrated circuit´s potential ESD discharge paths is critical to accurate utilization of the model. Quantitative prediction is achieved for HBM withstand voltages of an SRAM circuit. Optimization of protection-transistor layout area for a given ESD withstand level is discussed.