Outstanding challenges in testing nanotechnology based integrated circuits

Summary form only given. This presentation raises questions in all three dominant domains in the area of testing: traditional issues, power issues, and test application time issues. Traditional issues such as ATPG systems, fault simulators, and stuck-at faults are discussed, as well as new faults like capacitive and inductive crosstalks. The requirements in power delivery to the devices during normal operation as well as during test are expected to be largely in the area of test scheduling. Finally, the variable cost, the cost of testing each device, is likely to be dominated by the test application time. Hence, we need to develop novel solutions to the test application problem. This may mean re-looking at the most often used DFT and BIST methods. Also, we need to develop new and superior test generators and fault simulators that can handle faults from the new fault models for nanotechnologies and possibly deal with multiple faults.