A high performance IGBT with new n+buffer structure

Author

Takahashi, H. ; Ishimura, Y. ; Yokoyama, C. ; Hagino, H. ; Yamada, T.

Author_Institution

Mitsubishi Electr. Corp., Fukuoka, Japan

fYear

1995

fDate

23-25 May 1995

Firstpage

474

Lastpage

479

Abstract

An advanced IGBT with a new n+buffer structure has been developed. The new n+buffer structure is that some n+buried layers are formed at the boundary between a p+substrate and a n+buffer layer. The concentration of the n+buried layers is almost the same as that of the p+substrate. The fabrication of the IGBT with the new n+buffer structure used a 3rd gen 600 V/100 A chip. Taking the VVVF inverter as an application, total power loss generated was about 12% less compared to the conventional IGBT, only changing the n+buffer structure. And the short circuit safe operating area of the new IGBT was almost similar to the conventional IGBT. Moreover, we discussed differences between the new IGBT and the conventional IGBT using a 3D simulator, DAVINCI

Keywords

buried layers; insulated gate bipolar transistors; invertors; short-circuit currents; 100 A; 3D simulator; 600 V; DAVINCI; IGBT; VVVF inverter; fabrication; n+buffer; n+buried layers; p+substrate; power loss; short circuit; third generation chip; Circuit simulation; Electrodes; Fabrication; Insulated gate bipolar transistors; MOSFET circuits; Power generation; Tail; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs, 1995. ISPSD '95., Proceedings of the 7th International Symposium on

Conference_Location

Yokohama

ISSN

1063-6854

Print_ISBN

0-7803-2618-0

Type

conf

DOI

10.1109/ISPSD.1995.515084

Filename

515084