DocumentCode
2366974
Title
Study of gated pnp as an ESD protection device for mixed-voltage and hot-pluggable circuit applications
Author
Minh Toug ; Gauthier, Robert ; Gross, Vaughn
Author_Institution
Microelectron. Div., IBM Corp., Essex Junction, VT, USA
fYear
1996
fDate
10-12 Sept. 1996
Firstpage
280
Lastpage
284
Abstract
The ESD protection results of lateral-gated PNP transistors for various circuit applications are presented. Human body model (HBM) ESD performance was found to depend on the I/O scheme while wafer-level HBM ESD protection varied from 6.6 kV to 7.6 kV for hot-plug application and mixed-voltage application, respectively.
Keywords
electrostatic discharge; field effect transistors; protection; 6.6 to 7.6 kV; ESD protection device; I/O circuit; hot-pluggable circuit; human body model; lateral-gated PNP transistor; mixed-voltage circuit; Electrostatic discharges; FETs; Protection;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Overstress/Electrostatic Discharge Symposium, 1996. Proceedings
Print_ISBN
1-878303-69-4
Type
conf
DOI
10.1109/EOSESD.1996.865154
Filename
865154
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