Reducing scan shifts using folding scan trees

Author

Yotsuyanagi, Hiroyuki ; Kuchii, Toshimasa ; Nishikawa, Shigeki ; Hashizume, Masaki ; Kinoshita, Kozo

Author_Institution

Fac. of Eng., Tokushima Univ., Japan

fYear

2003

fDate

16-19 Nov. 2003

Firstpage

6

Lastpage

11

Abstract

In this paper, a new method for reducing scan shifts is presented. Scan design is one of the most popular design for test technologies for sequential circuits. However, it requires much test application time and test data when applied to circuits with many flip-flops. The new scan method utilizes two configurations of scan chains, a folding scan tree and a fully compatible scan tree. A test pattern including many don´t care values is used to configure a fully compatible scan tree in order to reduce the scan shift without degrading fault coverage. And then a folding scan tree is configured to reduce the length of the scan chain and thus reduce the scan shift. Experimental results for benchmark circuits shows this scan method can reduce many scan shifts.

Keywords

boundary scan testing; design for testability; logic design; logic testing; compatible scan tree; design for test; fault coverage; flip-flops; folding scan trees; scan chain length reduction; scan shift reduction; sequential circuits; test application time; test pattern don´t care values; Benchmark testing; Boundary scan testing; Circuit faults; Circuit testing; Degradation; Design for testability; Fault detection; Flip-flops; Informatics; Logic circuit testing; Logic design; Sequential analysis; Sequential circuits; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 2003. ATS 2003. 12th Asian

ISSN

1081-7735

Print_ISBN

0-7695-1951-2

Type

conf

DOI

10.1109/ATS.2003.1250772

Filename

1250772