Title :
Analyzing the impact of process variations on DRAM testing using border resistance traces
Author :
Al-Ars, Zaid ; Van de Goor, Ad J.
Author_Institution :
Fac. of Inf. Technol. & Syst., Delft Univ. of Technol., Netherlands
Abstract :
As a result of variations in the fabrication process, different memory components are produced with different operational characteristics, a situation that complicates the fault analysis process of manufactured memories. This paper discusses the issue of process variations, and shows how to deal with it in the context of fault analysis and test generation. The paper also introduces the concept of border resistance traces as a tool to optimize test stresses and inspect the impact of process variations on the optimization procedure. The concepts are discussed in the paper with the help of a practical example of a specific defect in the memory.
Keywords :
DRAM chips; automatic test pattern generation; fault simulation; integrated circuit testing; DRAM testing; border resistance traces; defect injection; different operational characteristics; electrical simulation; fault analysis method; folded cell array column; optimization procedure; process variations; test generation; test stresses; Computer aided manufacturing; Current measurement; DRAM chips; Fabrication; Information analysis; Information technology; Integrated circuit testing; Manufacturing processes; Random access memory; Semiconductor process modeling; Stress; Testing;
Conference_Titel :
Test Symposium, 2003. ATS 2003. 12th Asian
Print_ISBN :
0-7695-1951-2
DOI :
10.1109/ATS.2003.1250777
