Implementation of memory tester consisting of SRAM-based reconfigurable cells

Author

Yamagata, Yuki ; Ichino, Kenichi ; Arai, Masayuki ; Fukumoto, Satoshi ; Iwasaki, Kazuhiko ; Sato, Masayuki ; Itabashi, Hiroyuki ; Murai, Takashi ; Otsuka, Nobuyuki

Author_Institution

Graduate Sch. of Eng., Tokyo Metropolitan Univ., Japan

fYear

2003

fDate

16-19 Nov. 2003

Firstpage

28

Lastpage

31

Abstract

A scheme for testing SRAMs is proposed with a tester circuit consisting of SRAM-based reconfigurable cells. We first show an approach to reduce the number of reconfigurable cells required for the tester circuit. We then propose a tester for a 4 Mbit SRAM with reconfigurable cells of 16 bit data SRAMs. We also report the implementation of the proposed circuit. Four 16 bit reconfigurable cells, each of which consists of an SRAM and two CPLDs, were implemented, and mounted on a board. We confirmed that the tester functions correctly by performing a marching test.

Keywords

SRAM chips; counting circuits; integrated circuit testing; logic design; logic testing; programmable logic devices; 16 bit; 4 Mbit; CPLD; SRAM memory tester; SRAM testing; SRAM-based reconfigurable cells; marching test; shiftable latches; up-down counter; Circuit testing; Clocks; Costs; Counting circuits; Integrated circuit testing; Latches; Logic circuit testing; Logic design; Logic testing; Performance evaluation; Programmable logic devices; Random access memory; SRAM chips; Semiconductor device manufacture; Silicon compounds; Software testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 2003. ATS 2003. 12th Asian

ISSN

1081-7735

Print_ISBN

0-7695-1951-2

Type

conf

DOI

10.1109/ATS.2003.1250778

Filename

1250778