DocumentCode
2367138
Title
A heterogeneous hierarchical solution to cost-efficient high performance computing
Author
Miled, Z.B. ; Fortes, José A B
Author_Institution
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
fYear
1996
fDate
23-26 Oct 1996
Firstpage
138
Lastpage
145
Abstract
Two facts that suggest the desirability of a hierarchical approach to cost-effective high-performance computing are empirically established in this paper. The first fact is the temporal locality of programs with respect to the degree of parallelism. Two temporal (instruction and data) locality principles are identified and empirically established for a set of programs. The impact of this behavior is discussed with respect to the proposed heterogeneous multilevel architecture. The second fact that supports the hierarchical architecture is the cost-efficiency advantage of heterogeneous over homogeneous multiprocessor systems. An initial performance analysis is presented which quantifies this fact for the proposed heterogeneous hierarchical organization. The proposed multilevel processor configuration uses fast and costly resources sparingly to reduce sequential and low parallelism bottlenecks. The resulting organization tries to balance cost, speed and parallelism granularity
Keywords
parallel architectures; performance evaluation; heterogeneous hierarchical solution; heterogeneous multilevel architecture; hierarchical architecture; high performance computing; multilevel processor configuration; temporal locality of programs; Application software; Bridges; Computer applications; Concurrent computing; Costs; Environmental economics; High performance computing; Multiprocessing systems; Parallel processing; Research and development;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel and Distributed Processing, 1996., Eighth IEEE Symposium on
Conference_Location
New Orleans, LA
Print_ISBN
0-8186-7683-3
Type
conf
DOI
10.1109/SPDP.1996.570326
Filename
570326
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