DocumentCode
2367242
Title
3D electro-thermal modeling for ESD protection structures in Sub-100nm CMOS
Author
Lin, L. ; Wang, X. ; Liu, J. ; Wang, A. ; Liu, H. ; Zhou, Y. ; Yang, L.
Author_Institution
Dept. of Electr. Eng., Univ. of California, Riverside, Riverside, CA
fYear
2008
fDate
24-27 March 2008
Firstpage
520
Lastpage
523
Abstract
This paper reviews advances in new 3D electro-thermal modeling technique for ESD (electrostatic discharge) protection structures. New 3D ESD device modeling is critical to full-chip ESD protection circuit design synthesis, verification, optimization and prediction, especially for IC designs in sub 100 nm CMOS technologies.
Keywords
CMOS integrated circuits; electrostatic discharge; integrated circuit design; 3D ESD device modeling; CMOS; IC design; electro-thermal modeling; electrostatic discharge protection; full-chip ESD protection circuit design; size 100 nm; CMOS integrated circuits; CMOS technology; Circuit synthesis; Design optimization; Electrostatic discharge; Integrated circuit modeling; Integrated circuit synthesis; Predictive models; Protection; Semiconductor device modeling;
fLanguage
English
Publisher
ieee
Conference_Titel
Nanoelectronics Conference, 2008. INEC 2008. 2nd IEEE International
Conference_Location
Shanghai
Print_ISBN
978-1-4244-1572-4
Electronic_ISBN
978-1-4244-1573-1
Type
conf
DOI
10.1109/INEC.2008.4585540
Filename
4585540
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