DocumentCode
2367265
Title
Variance reduction in Monte Carlo capacitance extraction
Author
Batterywala, Shabbir H. ; Desai, Madhav P.
Author_Institution
Synopsys (India) Pvt. Ltd., Bangalore, India
fYear
2005
fDate
3-7 Jan. 2005
Firstpage
85
Lastpage
90
Abstract
In this article we address efficiency issues in implementation of Monte Carlo algorithm For 3D capacitance extraction. Error bounds in statistical capacitance estimation are discussed. Methods to tighten them through variance reduction techniques are detailed. Sample values in implementation of Monte Carlo algorithm are completely determined by the first hop in random walk. This in turn facilitates application of variance reduction techniques like importance sampling and stratified sampling to be used effectively. Experimental results indicate average speedup of 16X in simple uniform dielectric technologies, 7.3X in technologies with layers of dielectrics and 4.6X in technologies having conformal dielectrics.
Keywords
Monte Carlo methods; capacitance measurement; random processes; 3D capacitance extraction; Monte Carlo capacitance extraction; conformal dielectrics; dielectric layers; error bounds; importance sampling; random walk; statistical capacitance estimation; stratified sampling; uniform dielectric technologies; variance reduction; Boundary element methods; Capacitance; Dielectrics; Electrostatics; Finite element methods; Integral equations; Monte Carlo methods; Sampling methods; Signal analysis; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 2005. 18th International Conference on
ISSN
1063-9667
Print_ISBN
0-7695-2264-5
Type
conf
DOI
10.1109/ICVD.2005.169
Filename
1383258
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