A heuristic approach for design of easily testable PLAs using pass transistor logic

In this paper, an improved design of easily testable PLAs has been proposed, based on input decoder augmentation using pass transistor (PT) logic along with improved conditions for product line grouping. The proposed technique primarily increases the fault coverage area of easily testable PLAs due to augmented PT and reduced testing time due to grouping the product lines. A simultaneous testing technique has been applied within the group that reduces the testing time. This approach ensures the detection of certain bridging faults, which were not considered by the existing techniques. A modified testing technique has also been presented in this paper. It is shown that the new grouping technique enhances the devices in all respects.