Title :
20V-40V Symmetrical Vertical Trench nMOS (SVT MOS) design for display driver ICs
Author :
Annese, M. ; Montanini, P. ; Toia, F. ; Zullino, L. ; Contiero, C.
Author_Institution :
FTM-R&D Smart Power & High Voltage Technol. Platform Dev., STMicroelectronics, Agrate Brianza
Abstract :
This paper presents a novel 20V/40V symmetrical vertical trench MOS (SVT MOS) having both drain extension and gate realized in vertical direction respect to the silicon surface. Using silicon depth to realize the gate and to withstand high voltage, carefully designing doping implants and realizing a vertical field oxide, it was possible to reduce more than 60% the device pitch (i.e. spacing between half drain contact and half source contact) maintaining the same performance of equivalent lateral device
Keywords :
MOSFET; display devices; driver circuits; semiconductor doping; 20 V; 40 V; SVT MOS design; device pitch reduction; display driver integrated circuits; doping implant design; drain extension; half drain contact; half source contact; symmetrical vertical trench nMOS; vertical field oxide; CMOS technology; Displays; Doping; Driver circuits; Etching; Lithography; MOS devices; Silicon; Thin film transistors; Voltage;
Conference_Titel :
Power Semiconductor Devices and IC's, 2006. ISPSD 2006. IEEE International Symposium on
Conference_Location :
Naples
Print_ISBN :
0-7803-9714-2
DOI :
10.1109/ISPSD.2006.1666069
