DocumentCode :
236741
Title :
Electrical modeling and analysis of sidewall roughness of through silicon vias in 3D integration
Author :
Ehsan, M. Amimul ; Zhen Zhou ; Yang Yi
Author_Institution :
Dept. of Comput. Sci. & Electr. Eng., Univ. of Missouri-Kansas City, Kansas City, MO, USA
fYear :
2014
fDate :
4-8 Aug. 2014
Firstpage :
52
Lastpage :
56
Abstract :
Electrical modeling of through silicon via (TSV) is very important for three dimensional (3D) system design and analysis. In this paper, we present our study on the impact of sidewall roughness on the TSV electrical performance in the ultra-broad band range. Our analysis shows that the root mean square height of the rough sidewall is comparable to the skin depth in extremely high frequency (> 20G HZ). Therefore, the effect of TSV sidewall roughness becomes one of the critical factors to be considered when modeling TSV in extremely high frequency band. An electrical model of TSV is proposed considering the effect of TSV sidewall roughness, as well as capturing the high frequency skin effect. The proposed circuit model is analytically calculated and validated with EM field simulations up to 50 GHz.
Keywords :
electromagnetic fields; integrated circuit design; integrated circuit modelling; skin effect; three-dimensional integrated circuits; 3D integration; 3D system design; EM field simulations; TSV electrical performance; TSV sidewall roughness; electrical modeling; high frequency skin effect; root mean square height; skin depth; through silicon via; Analytical models; Integrated circuit modeling; Resistance; Silicon; Solid modeling; Three-dimensional displays; Through-silicon vias; 3D integration; EM field; RLGC parameter; TSV; equivalent circuit; rough sidewall; skin depth;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electromagnetic Compatibility (EMC), 2014 IEEE International Symposium on
Conference_Location :
Raleigh, NC
Print_ISBN :
978-1-4799-5544-2
Type :
conf
DOI :
10.1109/ISEMC.2014.6898942
Filename :
6898942
Link To Document :
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