Phase Noise Simulation and Modeling of ADPLL by SystemVerilog

Event driven phase noise simulation and modeling of an ADPLL by SystemVerilog is presented in this paper. It uses the simple Stochastic Voss-McCartney algorithm to generate the pink noise so that the 1/f phase noise effect can be easily modeled. Since the event driven simulation is extremely fast compared to the circuit level simulation, it allows circuit designers to explore different ADPLL architectures at the early stage without going through the time-consuming circuit level simulation. Pure SystemVerilog implementation also makes it possible to simulate the phase noise effect of the ADPLL efficiently in a large SOC system.