DocumentCode :
2367647
Title :
Ultra-thin chip technology for system-in-foil applications
Author :
Angelopoulos, Evangelos A. ; Zimmermann, Martin ; Appel, Wolfgang ; Endler, Stefan ; Ferwana, Saleh ; Harendt, Christine ; Hoang, Tu ; Pruemm, Andreas ; Burghartz, Joachim N.
Author_Institution :
Inst. for Microelectron. Stuttgart (IMS CHIPS), Stuttgart, Germany
fYear :
2010
fDate :
6-8 Dec. 2010
Abstract :
A new additive ultra-thin chip fabrication process is presented, utilizing an array of vertical anchors that mechanically connect silicon membrane chips to a standard silicon wafer. The process is demonstrated down to 8 μm silicon chip thickness, with a chip thickness control better than ±0.2 μm and a surface topography with average roughness <; 7 nm. Such pre-processed wafers can be used for CMOS manufacturing like any conventional silicon substrate. A wide process window with yield figures exceeding 99% is achieved by proper management of the built-in and externally applied stress on the anchors. The excellent mechanical flexibility and stability of these ultra-thin chips make them particularly suitable for system-in-foil applications.
Keywords :
CMOS integrated circuits; etching; flexible electronics; integrated circuit manufacture; surface topography; CMOS manufacturing; Si; silicon membrane chips; silicon wafer; size 8 mum; surface topography; system-in-foil; ultra-thin chip fabrication process; ultra-thin chip technology; wide process window;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting (IEDM), 2010 IEEE International
Conference_Location :
San Francisco, CA
ISSN :
0163-1918
Print_ISBN :
978-1-4424-7418-5
Electronic_ISBN :
0163-1918
Type :
conf
DOI :
10.1109/IEDM.2010.5703284
Filename :
5703284
Link To Document :
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