Title :
Delay testing of MOS transistor with gate oxide short
Author :
Renovell, M. ; Gallière, J.M. ; Azaïs, F. ; Bertrand, Y.
Author_Institution :
Sci. et Techniques du Languedoc, Univ. de Montpellier II, France
Abstract :
Gate Oxide Short defects are becoming predominant as technology is scaling down. Boolean and IDDQ testing of this defect has been widely studied but there is no paper dedicated to delay testing of this defect. So, this paper studies the delay behavior of Gate Oxide Short faults due to pinhole in the gate oxide. The objective of this paper is to give a detailed analysis of the behavior of the GOS defect taking into account the random parameter of the defect such as the GOS resistance and the GOS location. Because art accurate analysis is desired, the bi-dimensional array will be used. Because a complete analysis is desired, we derive characteristic of the GOS as a function of the GOS resistance and location.
Keywords :
CMOS integrated circuits; MOSFET; SPICE; fault simulation; integrated circuit testing; semiconductor device testing; short-circuit currents; HSPICE simulation; MOS transistor; bidimensional array; defect location; defect resistance; delay testing; equivalent single transistor; fault model; gate oxide pinhole; gate oxide short defects; random parameter; transistor defect; CMOS integrated circuits; Circuit faults; Delay; Impedance; Integrated circuit testing; MOSFETs; Resistors; Robots; SPICE; Semiconductor device modeling; Semiconductor device testing; Short circuit currents; Silicon; Testing; Voltage;
Conference_Titel :
Test Symposium, 2003. ATS 2003. 12th Asian
Print_ISBN :
0-7695-1951-2
DOI :
10.1109/ATS.2003.1250804
