Flash Memory Cell Compact Modeling Using PSP Model

In this work, a new compact Flash memory cell model is developed using Verilog-A. The PSP MOS description is used as a basis for the formulation of the conduction channel behavior. The floating gate potential is implicitly computed with an added charge neutrality relation that ensures a good convergence in DC analysis. In order to perform transient simulations, as programming or erasing operations, injection current equations have been implemented. In this presentation, the model is run in ELDO simulator and is characterized with ICCAP software. It has been validated on an advanced STMicroelectronics´ technology. The final objective of this work is to provide an accurate and scalable design tool.