Occurrence and Simulation of Index-3 DAEs in VLSI Circuits

In this paper we present a circuit configuration that generates an Index-3 DAE. Previous index analyses of analog circuits have proved that the DAE set modeling the circuit is at most Index-2. We show that certain behavioral models for transistors can generate an Index-3 DAE when a particular structural condition is satisfied. Most BDF methods are unstable for Index-3 DAEs, the DAE set has to be preconditioned via constraint differentiation or regularization to reduce the Index of the DAE. We present an efficient regularization procedure that can be applied to the Index-3 DAE generated by the transistor model. The occurrence condition and the regularization procedure can be checked for and performed at the netlist level. We show with examples how the modification improves the simulation process in terms of accuracy of the solution and improved convergence properties.