Author :
Franco, J. ; Kaczer, B. ; Eneman, G. ; Mitard, J. ; Stesmans, A. ; Afanas´ev, V. ; Kauerauf, T. ; Roussel, Ph J. ; Toledano-Luque, M. ; Cho, M. ; Degraeve, R. ; Grasser, T. ; Ragnarsson, L. -Å ; Witters, L. ; Tseng, J. ; Takeoka, S. ; Wang, W.E. ; Hoffman
Abstract :
6Å EOT Si0.45Ge0.55 pFETs with 10 year lifetime at operating conditions (VDD=1V) are demonstrated. Ultra-thin EOT is achieved by interfacial layer (IL) scavenging. Negative Bias Temperature Instability (NBTI) is alleviated using a high Ge fraction, a thick SiGe quantum well (QW) and a thin Si cap. Hot Carrier Injection (HCI) and Time Dependent Dielectric Breakdown (TDDB) are shown also to not constitute a showstopper for optimized SiGe devices.
Keywords :
Ge-Si alloys; MOSFET; hot carriers; semiconductor device breakdown; semiconductor device reliability; semiconductor quantum wells; EOT; NBTI lifetime target; SiGe; equivalent oxide thickness; hot carrier injection; interfacial layer scavenging; negative bias temperature instability; optimized reliability; pMOSFET; size 6 angstrom; time dependent dielectric breakdown;
