DocumentCode :
2367877
Title :
Syntactic transformation of assume-guarantee assertions: from sub-modules to modules
Author :
Basu, Prasenjit ; Dasgupta, Pallab ; Chakrabarti, P.P.
Author_Institution :
Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
fYear :
2005
fDate :
3-7 Jan. 2005
Firstpage :
213
Lastpage :
218
Abstract :
Assume-guarantee style assertions are increasingly being adopted by the design community. This paper addresses the task of transforming the assume-guarantee RTL properties of a set of submodules to a set of assume-guarantee properties of the parent module. Though this task is of considerable importance in the validation of large designs, current assertion specification languages do not admit a clean separation between a behavioral property of a module (the "guarantee") and the input restriction (the "assume") under which it is expected to hold, thereby making this task very complex. In this paper, we propose a logic called interactive linear temporal logic which provides a platform for expressing module-level specifications separating the input assumptions from the guarantee properties. Using this logic, we further show how assume-guarantee properties for individual modules can be composed, thereby facilitating hierarchical FPV of large designs.
Keywords :
formal specification; specification languages; temporal logic; RTL property; assertion specification languages; assume-guarantee assertions; behavioral property; input restriction; interactive linear temporal logic; module-level specifications; modules; syntactic transformation; Computer science; Design engineering; Explosions; Hardware design languages; Logic design; Logic testing; Open systems; Protocols; Signal design; Specification languages;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 2005. 18th International Conference on
ISSN :
1063-9667
Print_ISBN :
0-7695-2264-5
Type :
conf
DOI :
10.1109/ICVD.2005.154
Filename :
1383279
Link To Document :
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