Title :
Layout technique to alleviate soft failure for short pitch multi finger ESD protection devices
Author :
Okushima, Mototsugu ; Shinzawa, T. ; Morishita, Yasuyuki
Author_Institution :
NEC Electron. Corp., Kawasaki
Abstract :
This paper describes a layout technique to alleviate soft failure for short pitch multi finger ggMOS devices. Forming metal path parallel to the finger achieved 17-30% improvement in soft failure current without area penalty. Improvement of heat dissipation parallel to the finger is a possible explanation for this phenomenon.
Keywords :
MIS devices; electrostatic discharge; integrated circuit layout; heat dissipation; layout technique; short pitch multi finger ESD protection devices; short pitch multi finger ggMOS devices; soft failure current; Electronic ballasts; Electrostatic discharge; Fingers; Leakage current; National electric code; Network-on-a-chip; Protection; Pulse measurements; Resistors; Silicides;
Conference_Titel :
29th Electrical Overstress/Electrostatic Discharge Symposium, 2007. EOS/ESD
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-58537-136-5
DOI :
10.1109/EOSESD.2007.4401729
