A highly manufacturable integration technology for 27nm 2 and 3bit/cell NAND flash memory

Author

Lee, Choong-Ho ; Sung, Suk-Kang ; Jang, Donghoon ; Lee, Sehoon ; Choi, Seungwook ; Kim, Jonghyuk ; Park, Sejun ; Song, Minsung ; Baek, Hyun-Chul ; Ahn, Eungjin ; Shin, Jinhyun ; Shin, Kwangshik ; Min, Kyunghoon ; Cho, Sung-Soon ; Kang, Chang-Jin ; Choi, J

Author_Institution

Flash Dev. Center, Samsung Electron. Co., Hwasung, South Korea

fYear

2010

fDate

6-8 Dec. 2010

Abstract

A highly manufacturable multi-level NAND flash memory with a 27nm design rule has been successfully developed for the first time. Its unit cell size is 0.00375um² (with overhead). Self Aligned Reverse Patterning is used to improve initial Vth distribution induced from DPT (Double Patterning Technology) process. By using advanced channel doping technique, the channel junction leakage is minimized and the Vpass window is improved. The optimized doping structure and cell operation scheme are evaluated. And finally 2 and 3bit per cell operation are successfully demonstrated with flash cells of 32Gb density with reasonable reliability.

Keywords

NAND circuits; flash memories; logic design; NAND flash memory; channel doping technique; channel junction leakage; double patterning technology; integration technology; self aligned reverse patterning; wavelength 27 nm;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2010 IEEE International

Conference_Location

San Francisco, CA

ISSN

0163-1918

Print_ISBN

978-1-4424-7418-5

Electronic_ISBN

0163-1918

Type

conf

DOI

10.1109/IEDM.2010.5703299

Filename

5703299